概要

The 72V2105 is an 256K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.

72V2105 - Block Diagram
72V2105 - Block Diagram
  • Pin-compatible with the 72V2x5 SuperSync FIFOs
  • 10ns read/write cycle time (6.5ns access time)
  • Fixed, low first word data latency time
  • 5V input tolerant
  • Auto power down minimizes standby power consumption
  • Retransmit operation with fixed, low first word data latency time
  • Empty, Full and Half-Full flags signal FIFO status
  • Programmable Almost-Empty and Almost-Full flags, Easily expandable in depth and width
  • Independent Read and Write clocks (permit reading and writing simultaneously)
  • Available in a 64-pin TQFP package
  • Industrial temperature range (–40C to +85C) is available

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    72V2105L10PFG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		TQFP 64 C Yes Tray 3 168.54 サンプルを入手,
    72V2105L15PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 64 I Yes Tray 3 168.54 サンプルを入手,
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