概要

The 72V215 is a 512 x 18 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72215 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.

72V215 - Block Diagram
72V215 - Block Diagram
  • 10ns read/write cycle time
  • 5V input tolerant
  • Renesas Standard or First Word Fall Through timing
  • Single or double register-buffered Empty and Full flags
  • Easily expandable in depth and width
  • Asynchronous or coincident Read and Write clocks
  • Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings
  • Half-Full flag capability
  • Output enable puts output data bus in a high-impedance state
  • Available in 64-pin TQFP and STQFP packages
  • Industrial temperature range (–40 °C to +85 °C) is available

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    72V215L10TFG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		TQFP 64 C Yes Tray 3 サンプルを入手,
    72V215L10TFG8
    circleアクティブ
    memory
    view_in_ar
    		TQFP 64 C Yes Reel 3
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