概要

The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

72V281 - Block Diagram
72V281 - Block Diagram
  • Pin-compatible with the 72V2x1and IDT72V21x1 SuperSync FIFOs
  • Functionally compatible with the 5 Volt 72281
  • 10ns read/write cycle time (6.5ns access time)
  • Fixed, low first word data latency time
  • Auto power down minimizes standby power consumption
  • Retransmit operation with fixed, low first word data latency time
  • Empty, Full and Half-Full flags signal FIFO status
  • Programmable Almost-Empty and Almost-Full flags
  • Easily expandable in depth and width
  • Independent Read and Write clocks (permit reading and writing simultaneously)
  • Available in 64-pin TQFP and STQFP packages
  • Industrial temperature range (–40C to +85C) is available

ドキュメント

設計・開発

ECADモデル

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    72V281L15PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 64 I Yes Tray 3 95.21 サンプルを入手,
    72V281L15TFGI
    circleアクティブ
    memory
    view_in_ar
    		TQFP 64 I Yes Tray 3 95.8
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