概要

The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible bus-matching x36/x18/x9 data flow and asynchronous/synchronous translation on the read or write ports. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

72V36110 - Block Diagram
72V36110 - Block Diagram
  • Pin-compatible with the SuperSync II 72V36x0 family
  • Up to 166MHz operation of the clocks
  • User-selectable asynchronous read and/or write ports (PBGA only)
  • User-selectable input and output port bus-sizing
  • 5V input tolerant
  • Auto power-down minimizes standby power consumption
  • Master Reset clears the entire FIFO
  • Partial Reset clears the data, but retains programmable settings
  • Easily expandable in depth and width
  • JTAG port, provided for Boundary Scan function (PBGA only)
  • Independent Read and Write clocks
  • Available in 128-pin TQFP or 144-pin PBGA packages
  • Industrial temperature range (–40 °C to +85 °C) is available

ドキュメント

設計・開発

ECADモデル

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    72V36110L6PFG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		TQFP 128 C Yes Tray 3 186.58 サンプルを入手,
    72V36110L7-5PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		TQFP 128 I Yes Tray 3 186.85 サンプルを入手,
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