概要
説明
The 9FGL0641/51 devices are 6-output 3.3V PCIe Gen 1–6 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0641/51 supports PCIe Gen 1–6 Common Clocked architectures (CC), PCIe Separate Reference no Spread (SRNS), and Separate Reference Independent Spread (SRIS) clocking architectures.
For information regarding evaluation boards and material, please contact your local sales representative.
特長
- PCIe Gen 1–6 CC-compliant
- Supports PCIe SRIS and SRNS clocking
- Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
- Pin-selectable SRNS 0%, CC 0%, and CC/SRIS -0.5% spread
- SMBus-selectable CC/SRIS -0.25% spread
- One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
- Easy AC coupling to other logic families, see application note AN-891.
- Space saving 5mm × 5mm 40-VFQFPN
製品比較
アプリケーション
アプリケーション
- Servers/High-Performance Computing
- nVME Storage
- Networking
- Accelerators
- Industrial Control
設計・開発
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モデル
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ビデオ&トレーニング
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
ニュース＆ブログ
| ブログ | 2022年4月14日 | ||
| ブログ | 2018年5月22日 | ||
| ニュース | 2018年4月30日 | ||
| IDT社、世界最小電力のPCI Expressタイミング・ファミリに 3.3 V PCIeクロックジェネレータを追加 | ニュース | 2015年6月23日 |
