概要
説明
Provides 48 PCIe Gen2 lanes and 12 ports of high-performance, deterministic system interconnect switching. All ports receive full line rate, non-blocking throughput for multiple traffic flows regardless of switch loading.
特長
- 48 PCIe Gen2 Lanes, 12 Switch Ports
- Non-blocking switch architecture optimized for High Performance System Interconnect
- Partionable switch architecture for true multi-root support
- Internal buffering and flow control credits optimized for maximum bandwidth and large payloads
- Low latency, Low power
製品比較
アプリケーション
設計・開発
Processing table
| FCBGA | 676 | C | No | Tray | ||
| FCBGA | 676 | C | No | Reel | ||
| FCBGA | 676 | C | Yes | Tray | ||
| FCBGA | 676 | C | Yes | Reel | ||
| FCBGA | 676 | I | Yes | Tray | ||
| FCBGA | 676 | I | Yes | Reel | ||
| FCBGA | 676 | I | No | Tray | ||
| FCBGA | 676 | I | No | Reel |
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