概要
説明
The 9DB833 zero delay buffer (ZDB) supports PCIe Gen3 requirements while being backward compatible with PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from a 932S421 or 932SQ420 or equivalent main clock generator.
特長
- Eight 0.7V HCSL differential output pairs
- Phase jitter: PCIe Gen3 < 1ps rms
- Phase jitter: PCIe Gen2 < 3.1ps rms
- Phase jitter: PCIe Gen1 < 86ps peak-to-peak
- Supports Zero Delay Buffer mode and Fanout mode
- Bandwidth programming available
- 3 selectable SMBus Addresses
- 50MHz to 110MHz operation in PLL mode
- 5MHz to 166MHz operation in Bypass mode
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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ビデオ&トレーニング
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List
