概要
説明
The 9FGV0231 is a 2-output very-low power clock generator for PCIe Gen 1–4 Common Clocked (CC) applications. The device has two output enables for clock management and supports two different spread spectrum levels in addition to spread off.
特長
- PCIe Gen 1–4 CC-compliant
- 1.8V operation: reduced power consumption
- OE# pins: support DIF power management
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- DIF outputs are blocked until PLL is locked: clean system start-up
- Selectable 0%, -0.25%, or -0.5% spread on DIF outputs: reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins: SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 4mm x 4mm 24-pin VFQFPN; minimal board space
製品比較
アプリケーション
- PCIe Gen 1-4 clock generation
- Riser cards
- Storage
- Networking
- JBOD
- Communications
- Access points
設計・開発
モデル
ECADモデル
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ビデオ&トレーニング
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
