概要

The 9FGV0631 is a member of IDT's SOC-Friendly 1.8 V Very-Low-Power PCIe clock family. The device has 6 output enables for clock management, 2 different spread spectrum levels in addition to spread off and 2 selectable SMBus addresses.

9FGV0631 Block Diagram
9FGV0631 Pinout Diagram
9FGV0631 Block Diagram
9FGV0631 Pinout Diagram
  • PCIe Gen1–4 compliant
  • LP-HCSL outputs; save 12 resistors compared to standard PCIe devices
  • 54 mW typical power consumption; reduced thermal concerns
  • Outputs can optionally be supplied from any voltage between 1.05 and 1.8 V; maximum power savings
  • OE# pins; support DIF power management
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
  • External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface works with legacy controllers
  • Space saving 5x5 mm 40-pin VFQFPN; minimal board space
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment
     

ドキュメント

設計・開発

ECADモデル

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9FGV0631CKILF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 40 I Yes Tray
    9FGV0631CKILFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 40 I Yes Reel
    9FGV0631CKLF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 40 C Yes Tray
    9FGV0631CKLFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 40 C Yes Reel
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