概要
説明
The 9QXL2000C is a 20-output very-low additive phase jitter fanout buffer for PCIe Gen1 through Gen6. It offers integrated terminations for 85Ω transmission lines.
特長
- Low-Power HCSL (LP-HCSL) 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
- Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
- 8 OE# pins configurable to control up to 20 outputs
- 9 selectable SMBus addresses
- Spread spectrum compatible
- 10mm × 10mm 72-VFQFPN package
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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| VFQFPN | 72 | -40 to 105°C | Yes | Tray | 3 | サンプルを入手, | |
| VFQFPN | 72 | -40 to 105°C | Yes | Reel | 3 |
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ビデオ&トレーニング
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.