概要
説明
The 524S is a low skew, single input to four output, LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.
特長
- Low additive phase jitter RMS: 50fs
- Extremely low skew outputs (50ps)
- Low-cost clock buffer
- Packaged in an 8-SOIC and 8-DFN, Pb-free
- ICLK is PDT and may be driven before VDD is applied
- Direct-coupled signal path suitable for 1pps clocks
- Input/Output clock frequency up to 200MHz
- Non-inverting output clock
- Ideal for networking clocks
- Operating voltages: 1.8V to 3.3V
- Advanced, low-power CMOS process
- Extended temperature range: -40 °C to +105 °C
製品比較
アプリケーション
ドキュメント
ピックアップ
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| 分類 | タイトル | 日時 |
| データシート | PDF 267 KB | |
| アプリケーションノート | PDF 187 KB | |
| 概要 | PDF 217 KB | |
| 製品変更通知 | PDF 268 KB | |
| 製品変更通知 | PDF 611 KB | |
| 製品変更通知 | PDF 611 KB | |
| アプリケーションノート | PDF 495 KB | |
| アプリケーションノート | PDF 442 KB | |
| アプリケーションノート | PDF 565 KB | |
9件
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設計・開発
モデル
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ビデオ&トレーニング
Low-jitter LVCMOS Fanout Clock Buffers by IDT
This video overviews the LVCMOS Fanout Buffers, showcasing their best-in-class performance with extremely low phase jitter, minimal output skew, and low power consumption, along with other competitive features.
Video List
