概要

The 854S054I is a 4:1 differential-to-LVDS clock multiplexer that can operate up to 2.5GHz. The 854S054I has four selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pull-down resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).

854S054I - Block Diagram
854S054I - Pinout
854S054I - Block Diagram
854S054I - Pinout
  • High-speed 4:1 differential multiplexer
  • One differential LVDS output pair
  • Four selectable differential PCLK, nPCLK input pairs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML
  • Maximum output frequency: 2.5GHz
  • Translates any single-ended input signal to LVDS levels with resistor bias on nPCLKx input
  • Additive phase jitter, RMS: 0.147ps (typical)
  • Part-to-Part skew: 300ps (maximum)
  • Propagation delay: 700ps (maximum)
  • Supply voltage range: 3.135V to 3.465V
  • -40 °C to 85 °C ambient operating temperature
  • Available in a lead-free (RoHS 6) package

ドキュメント

設計・開発

ECADモデル

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製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    854S054AGILF
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TSSOP 16 I Yes Tube 1 10.8 サンプルを入手,
    854S054AGILFT
    circleアクティブ
    memory
    view_in_ar
    		TSSOP 16 I Yes Reel 1
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