概要

This is the evaluation kit for the Renesas RC32614A ClockMatrix System Synchronizer for IEEE 1588. The RC32614A provides six independent timing channels that can be configured as Digital PLLs (DPLLs) or as Digitally Controlled Oscillators (DCOs). The DPLL channels meet synchronous Ethernet requirements and they can be used for jitter attenuation and frequency translation. The DCOs they can be programmed to synthesize the desired frequency and can be steered by external software with resolution of  1.11E-16. The DPLLs can lock to virtually any frequency from 0.5Hz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 0.5Hz to 1GHz with ultra-low phase noise <100fs RMS from 12kHz to 20MHz. 

8A34xxx - 144BGA Evaluation Board (top)
8A34xxx - 144BGA Evaluation Board (perspective)
8A34xxx - 144BGA Evaluation Board (top)
8A34xxx - 144BGA Evaluation Board (perspective)
  • 4 differential clock inputs
  • 14 differential outputs
  • 2 serial port channels
  • On-board EEPROM
  • On-board miniOCXO
  • 16 GPIO controls
  • Selectable voltage controls

ドキュメント

= ピックアップ
分類 タイトル 日時
マニュアル－ハードウェア
RC32614A-EVK Evaluation Board Manual
PDF 1.59 MB
回路図
RC32614 Evaluation Board Schematic
ログインしてダウンロード PDF 445 KB
2件

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