概要

This is the evaluation kit for the RC32012A FemtoClock Jitter Attenuator and Clock Generator. The RC32012A provides two independent timing channels that can be configured as Digital PLLs (DPLLs) or as Digitally Controlled Oscillators (DCOs) and with up to four independent frequency domains that are each either locked to the external reference input or locked to free-run crystal or oscillator. The DPLL channels meet synchronous Ethernet and wireless radio clocking requirements and they can be used for jitter attenuation and frequency translation. The DCOs they can be programmed to synthesize the desired frequency and can be steered by external software with resolution of  1.11E-16. The DPLLs can lock to virtually any frequency from 0.5Hz to 1GHz and the DPLLs and DCOs can generate virtually any frequency from 0.5Hz to 1GHz with typical jitter below 120fs RMS from 12kHz to 20MHz in jitter attenuator mode and below 100fs RMS from 12kHz to 20MHz in clock generator mode. 

  • 2 differential clock inputs
  • 12 differential outputs
  • 2 serial port channels
  • On-board EEPROM
  • On-board miniOCXO
  • 16 GPIO controls
  • Selectable voltage controls

ドキュメント

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分類 タイトル 日時
データシート
RC32012A Datasheet
PDF 2.57 MB
Other
RC32012A Schematic Checklist
XLSX 394 KB
マニュアル－ハードウェア
RC32012A Evaluation Kit Manual
PDF 11.03 MB
3件

製品選択

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    RC32012A-EVK
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