概要

The 72V231 is a 2K x 9 First-In, First-Out (FIFO) memory with clocked read and write controls. It is a 3.3V version of the 72231 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks, and interprocessor communication. The 72V231 has 9-bit input and output ports. The Read Clock (RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronously of one another for dual clock operation.

72V231 - Block Diagram
72V231 - Block Diagram
  • 10ns read/write cycle time
  • 5V input tolerant
  • Read and Write clocks can be independent
  • Dual-ported zero fall-through time architecture
  • Empty and Full Flags signal FIFO status
  • Programmable Almost-Empty and Almost-Full flags can be set to any depth
  • Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively
  • Output Enable puts the output data bus in a high-impedance state
  • Available in 32-pin PLCC and TQFP packages
  • Industrial temperature range (–40 °C to +85 °C) is available

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    72V231L15PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 32 I Yes Tray 3 サンプルを入手,
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