概要

The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin.

71V67603 - Block Diagram
71V67603 - Block Diagram
  • High system speed 166MHz (3.5ns clock access time)
  • LBO input selects interleaved or linear burst mode
  • Self-timed write cycle with global write control (GW), byte
  • write enable (BWE), and byte writes (BWx)
  • 3.3V core power supply
  • Power down controlled by ZZ input
  • 3.3V I/O supply (VDDQ)
  • Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V67603S133PFG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 C Yes Tray 3 23.16 サンプルを入手,
    71V67603S133PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 25.32 サンプルを入手,
    71V67603S150PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 サンプルを入手,
    Parametric Table tips

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