概要

The 9DB202-01 is a high performance 1-to-1 Differential-to HCSL Jitter Attenuator designed for use in PCI Express®™ systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board.

9DB202-01 - Block Diagram
9DB202-01 - Pinout
9DB202-01 - Block Diagram
9DB202-01 - Pinout
  • One 0.7V current mode differential HCSL output pair
  • One differential clock input
  • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 140MHz
  • Input frequency range: 90MHz - 140MHz
  • VCO range: 450MHz - 700MHz
  • Cycle-to-cycle jitter: 30ps (maximum)
  • RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.31ps (typical)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free RoHS compliant package
  • Industrial temperature information available upon request

ドキュメント

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分類 タイトル 日時
データシート
9DB202-01 Datasheet
PDF 304 KB
EOL通知
PDN#: N-16-02 PRODUCT DISCONTINUANCE NOTICE ON SELECT DEVICES
PDF 161 KB
製品変更通知
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location
PDF 596 KB
製品変更通知
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location
PDF 544 KB
製品変更通知
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products
PDF 361 KB
5 items

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9DB202CK-01LF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 32 C Yes Tray
    9DB202CK-01LFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 32 C Yes Reel
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    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview