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説明

The 8SLVD1204 is a high-performance differential LVDS fanout buffer designed for the fanout of high-frequency, very-low additive phase noise clock and data signals. The 8SLVD1204 is characterized for operation from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1204 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low-skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

For a 3.3 V version of this device, please refer to the 8SLVD1204-33I.

特長

  • Four low-skew, low additive jitter LVDS output pairs
  • Two selectable differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
  • Maximum input clock frequency: 2GHz
  • LVCMOS/LVTTL interface levels for the control input select pin
  • Output skew: 20ps (maximum)
  • Propagation delay: 300ps (maximum)
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz to 20MHz: 95fs (maximum)
  • Full 2.5V supply voltage
  • Lead-free (RoHS 6), 16-lead VFQFN packaging
  • -40 °C to 85 °C ambient operating temperature

製品比較

アプリケーション

 

モデル

ECADモデル

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Diagram of ECAD Models
 
 
Low-jitter Differential Fanout Buffers - 8SLVP and 8SLVD Families from IDT
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