概要

The RC32514A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC, or FPGA that requires several reference clocks with a jitter performance of less than 100fs. The RC32514A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up, and/or frequency translation of a centrally-supplied reference, a synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a digitally controlled oscillator (DCO) for frequency margining or OTN clock applications. It contains an internal crystal that can be leveraged as the frequency reference for the onboard PLL if desired.

RC32514A - Block Diagram
RC32514A - Pin Assignment
RC32514A - Block Diagram
RC32514A - Pin Assignment
  • Jitter below 100fs RMS (10kHz to 20MHz)
  • Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
  • PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
    • Operates from an internal crystal
    • APLL frequency independent of input/crystal frequency
    • Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO)
    • DPLL loop filter programmable from 0.1Hz to 12kHz
    • DCO has a tuning granularity of < 1ppb
  • Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
    • Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS)
    • Reference monitor qualifies/disqualifies input clock
  • Programmable status output
  • 4 differential/8 LVCMOS outputs
    • Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
    • Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS
    • Differential output swing is selectable: 400mV to 800mV
    • Output clock phase individually adjustable in 100ps steps
    • Output Enable input with programmable effect
  • Supports up to 1MHz I²C or up to 20MHz SPI serial processor port
  • Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
  • 4mm × 4mm 28-VFQFPN package

ドキュメント

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RC32514A-EVK - Evaluation Board (front)

RC32514A-EVK

Evaluation
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FemtoClock™ 2 Evaluation Kit

This is the evaluation kit for the RC32514A and RC22514A. The board will come populated with an RC32514. The RC22514 is functionally a subset of the RC32514A, so this...

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FemtoClock®2 GUI User Guide

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製品選択

本デバイスは、ルネサス事業所でのプログラム書き込みが可能です。カスタムプログラムユーティリティをお試しください。
    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Range
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    ご購入 / サンプル
    型名
    RC32514A000GNL#BB0
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 VFQFPN 28 -40 to 85°C I Yes Tray 3 サンプルを入手,
    RC32514A000GNL#KB0
    circleアクティブ
    memory
    view_in_ar
    		VFQFPN 28 -40 to 85°C I Yes Reel 3
    Parametric Table tips

    Tips for Using This Parametric Table:

    • Hide Filters button in header: Collapse or expands filters
    • Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
    • Reset button in header: Reset all filters to the page default
    • Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
    • Export button in header: Export the filtered results of the table to an Excel document
    • Filter parts search bar in header: Type to filter table results by part number
    • Hide column button in column headers: Select to hide columns in table
    • AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
    • Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
    • Document icon next to product name in row: View the featured document for this product
    • Chip icon next to the right of the document icon in row: View the block diagram for this product
    • Cart icon to the right of the chip icon: Indicates that samples are available for this product

    ビデオ&トレーニング

    Lab on the Cloud Demo for FemtoClock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator

    Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.

    Video List
    Lab on the Cloud Demo for FemtoClock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator
    FemtoClock2 Portfolio of Industry’s Smallest, Lowest Power 75fs Jitter Clocks

    ニュース＆ブログ

    ブログ 2021年4月27日
    ブログ 2019年6月14日
    IDT、100Gと400Gアプリケーション向けに、 業界をリードする位相ノイズ性能の最新タイミング製品を発表 ニュース 2017年12月20日
    クラス最高の低ジッター性能で今日の要求の厳しいアプリケーションに応える IDT の12出力クロックジェネレータ ニュース 2016年8月2日