ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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RG5R256

アクティブ

DDR5 Register Command Address up to 5600MT/s

ご購入
RG5R256A1C0GBY Short-Form Datasheet

概要

The RG5R256 (Gen 2 RCD) is a registering clock driver used on DDR5 RDIMMs, LRDIMMs and NVDIMMs. It supports DDR5 server speeds up to 5600 MT/s. Its primary function is to buffer the Command Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. It also creates a BCOM bus to control the data buffers for LRDIMMs.

The RG5R256 contains two separate channels with some common logic such as clocking, but otherwise operate independently of each other. Each channel has a 7-bit double data rate CA bus input, a single parity input, two chip-select inputs, produces two copies of 14-bit single data rate CA bus outputs and two copies of the chip-select outputs. The RCD has a common clock input and PLL, but produces separate clock outputs to the DRAM channels.

RG5R256 - Block Diagram
RG5R256 - Block Diagram
  • Pinout optimized DDR5 RDIMM and LRDIMM PCB layout
  • DDR5 server speeds up to 5600MT/s
  • Supports power-down modes to conserve server power
  • Supports 1-rank/2-rank DIMM configurations
  • Supports SDP, DDP, 3DS DRAM types
  • Supports up to 16Gb DRAM die
  • Provides access to internal control words for configuring device features and adapting to different RDIMM and LRDIMM system applications
  • I2C and I3C sideband access for register access control
  • BCOM for LRDIMM data buffer control
  • Loopback and pass-through modes
  • Package: 8.7 × 13.5 mm, 240-FCBGA
  • RDIMM, LRDIMM and NVDIMM modules for Enterprise Servers
  • Memory down server motherboards

ドキュメント

ピックアップ
分類 タイトル 日時
データシート－簡略版
RG5R256A1C0GBY Short-Form Datasheet
PDF 159 KB
製品変更通知
PCN# : 240006 Add alternate assembly location on select devices from FCCSP-240
PDF 925 KB
製品変更通知
PCN# : 230019 Add alternate assembly location on select devices from FCCSP-240
PDF 924 KB
製品変更通知
PCN# : 230002 Add ASEC, Taiwan as Alternate Test Location
PDF 291 KB
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