概要

説明

The 5962-38294 (7164) SRAM is organized as 8K x 8 and offers a reduced power standby mode. The low-power version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation.

特長

  • High-speed address/chip select access time -20/25/35/45/55/70ns (max.)
  • Low power consumption
  • Battery backup operation – 2V data retention voltage
  • Produced with advanced CMOS high-performance technology
  • Inputs and outputs directly TTL-compatible
  • Three-state outputs
  • Available in 28-pin (300-mil or 600-mil) ceramic DIP packages
  • Military product compliant with MIL-STD-883, Class B

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