概要
説明
The 71256 5V CMOS SRAM is organized as 32K x 8. The circuit also offers a reduced power standby mode for significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Military grade product is available.
特長
- High-speed address/chip select time – Military: 25/35/45/55/70/85/100ns (max.)
- Commercial/Industrial: 20/25/35ns (max.) low power only
- Low-power operation
- Battery Backup operation – 2V data retention
- Input and output directly TTL-compatible
- Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (300 mil) SOJ
- Military product compliant to MIL-STD-883, Class B
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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Processing table
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
ご購入 / サンプル |
|
|---|---|---|---|---|---|---|---|---|
| 型名 | ||||||||
| CDIP | 28 | M | No | Tube | 1 | 31.54 |
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