概要

The 71V35761 3.3V CMOS SRAM is organized as 128K x 36. It contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V35761 can provide four cycles of data for a single address presented to the SRAM.

71V35761 - Block Diagram
71V35761 - Block Diagram
  • High system speed 200MHz (3.1ns clock access time)
  • LBO input selects interleaved or linear burst mode
  • Self-timed write cycle with global write control (GW), byte write
  • enable (BWE), and byte writes (BWx)
  • 3.3V core power supply
  • Power down controlled by ZZ input
  • 3.3V I/O
  • Optional - Boundary Scan JTAG Interface (IEEE 1149.1
  • compliant)
  • Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V35761S166PFG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 C Yes Tray 3 5.65 サンプルを入手,
    71V35761S166PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 サンプルを入手,
    71V35761SA166BGG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 PBGA 119 C Yes Tray 3 9.561 サンプルを入手,
    71V35761SA166BGG8
    circleアクティブ
    memory
    view_in_ar
    		PBGA 119 C Yes Reel 3 8.712
    71V35761SA166BQGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    今すぐ購入する
    		CABGA 165 I Yes Tray 3 9.012 サンプルを入手,
    71V35761SA166BQGI8
    circleアクティブ
    memory
    view_in_ar
    		CABGA 165 I Yes Reel 3
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