概要

The 71V3577 3.3V CMOS SRAM is organized as 128K x 36 and contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.

71V3577 - Block Diagram
71V3577 - Block Diagram
  • Fast access times - 7.5ns up to 117MHz clock frequency
  • LBO input selects interleaved or linear burst mode
  • Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
  • 3.3V core power supply
  • Power down controlled by ZZ input
  • 3.3V I/O
  • Optional - Boundary Scan JTAG interface (IEEE 1149.1 compliant)
  • Available in 100-pin TQFP, 119-pin BGA, and 165 fpBGA packages

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V3577S75BQG
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 CABGA 165 C Yes Tray 3 8.048 サンプルを入手,
    71V3577S75BQG8
    circleアクティブ
    memory
    view_in_ar
    		CABGA 165 C Yes Reel 3
    71V3577S80BGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 PBGA 119 I No Tray 3 9.777 サンプルを入手,
    71V3577S85PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 7.506 サンプルを入手,
    Parametric Table tips

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