概要

The 71T75902 2.5V CMOS Synchronous SRAM organized as 1M x 18 (18 Megabit). It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround.

71T75902 - Block Diagram
71T75902 - Block Diagram
  • Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access)
  • ZBTTM Feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (READ/WRITE) control pin
  • 4-word burst capability (Interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 2.5V power supply (±5%)
  • 2.5V (±5%) I/O Supply (VDDQ)
  • Power down controlled by ZZ input
  • Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
  • Available in 100-pin TQFP and 119-pin BGA packages

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71T75902S75PFGI
    circleアクティブ
    memory
    view_in_ar
    サンプル入手可能
    		 TQFP 100 I Yes Tray 3 37.97 サンプルを入手,
    71T75902S75PFGI8
    circleアクティブ
    memory
    view_in_ar
    		TQFP 100 I Yes Reel 3 33.15
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