概要

The 71V3558 3.3V CMOS synchronous SRAM, organized as 256K x 18, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V3558 contains data I/O, address, and control signal registers.

71V3558 - Block Diagram
71V3558 - Block Diagram
  • Supports high-performance system speed - 200MHz (x18) (3.2ns Clock-to-Data access)
  • ZBT feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (Read/Write) control pin
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
  • 4-word burst capability (interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
  • Optional- Boundary Scan JTAG interface (IEEE 1149.1 compliant)
  • Available in 100-pin TQFP and 165 fpBGA packages

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V3558S133PFGI
    circleアクティブ
    memory
    view_in_ar
    		TQFP 100 I Yes Tray 3
    71V3558S133PFGI8
    circleアクティブ
    memory
    view_in_ar
    		TQFP 100 I Yes Reel 3 9.106
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