概要

The 71V546 3.3V CMOS SRAM, organized as 128K x 36 bits, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V546 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

71V546 - Block Diagram
71V546 - Block Diagram
  • Supports high-performance system speed - 133MHz (4.2ns Clock-to-Data access)
  • ZBT feature - No dead cycles between write and read cycles
  • Internally synchronized registered outputs eliminate the need to control OE
  • Single R/W (Read/Write) control pin
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
  • 4-word burst capability (interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • Single 3.3V power supply (±5%)
  • Available in a 100-pin TQFP package

ドキュメント

設計・開発

ECADモデル

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    71V546S133PFGI
    circleアクティブ
    memory
    view_in_ar
    		TQFP 100 I Yes Tray 3 10.07
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