概要
説明
The 71V65603 3.3V CMOS SRAM, organized as 256K X 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65603 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.
特長
- High-performance system speed - 150MHz (3.8ns Clock-to-Data access)
- ZBT feature - No dead cycles between write and read cycles
- Internally synchronized output buffer enable eliminates the need to control OE
- Single R/W (Read/Write) control pin
- Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
- 4-word burst capability (interleaved or linear)
- Individual byte write (BW1 - BW4) control (May tie active)
- Three chip enables for simple depth expansion
- 3.3V power supply (±5%)
- 3.3V I/O Supply (VDDQ)
- Power down controlled by ZZ input
- Available in 100-pin TQFP, 119-pin BGA, and 165 fpBGA packages
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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Processing table
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
ご購入 / サンプル |
|
|---|---|---|---|---|---|---|---|---|
| 型名 | ||||||||
| TQFP | 100 | C | Yes | Tray | 3 | 16.22 | サンプルを入手, | |
| TQFP | 100 | C | Yes | Reel | 3 | |||
| CABGA | 165 | C | Yes | Tray | 3 | 13.86 | サンプルを入手, | |
| TQFP | 100 | C | Yes | Tray | 3 | 10.15 | サンプルを入手, | |
| TQFP | 100 | C | Yes | Reel | 3 | 9.172 | ||
| CABGA | 165 | I | Yes | Tray | 3 | 24.15 | サンプルを入手, | |
| CABGA | 165 | I | Yes | Reel | 3 |
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