ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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5T9302

廃止品

2.5V LVDS,1:2 Clock Buffer Terabuffer™

5T9302I Data Sheet
以下のデバイスを代替品として推奨しております。
8SLVP1102 - 1:2 LVPECL Output Fanout Buffer

概要

The 5T9302 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs. The fanout from a differential input to two LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9302 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 5T9302 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

5T9302 - Block Diagram
5T9302 - Pinout
5T9302 - Block Diagram
5T9302 - Pinout
  • Guaranteed low skew: 5ps (typical)
  • Very low duty cycle distortion: 20ps (typical)
  • High speed propagation delay: 1.35ns (typical)
  • Up to 450MHz operation
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface
  • Selectable differential inputs to two LVDS outputs
  • Power-down mode
  • 2.5V VDD
  • 0°C to 70°C ambient operating temperature
  • Available in TSSOP package

ドキュメント

設計・開発

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