概要
説明
The 9SQ440 is an Intel CK440 main clock synthesizer for Intel cloud and HPC platforms, and newer Intel-based server platforms. 9SQ440 is a single-chip, PCIe Gen6 compliant, and is designed to work as a complete clock solution or in combination with DB2000Q-compliant clock buffers to provide point-to-point clocks to multiple receiving agents.
特長
- PCIe Gen6 phase jitter < 40fs rms
- 3 x 25MHz dedicated output pairs
- 7 x 100MHz dedicated output pairs with individual OE# pins
- 9 MXCLK output pairs multiplexable between 100MHz and 25MHz
- 3.3V operation
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 80 resistors, saving 130mm2 of area
- 9 selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- OE# pin control of 100M[6:0] supports PCIe slot CLKREQ#
- Dedicated Platform Time input and output clocks (PFT_IN and PFT_OUT)
- 8 × 8 mm dual-row 100-VFQFPN
- -40°C to +85°C operating temperature range
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
[製品選択]テーブル内の製品名をクリックするとSamacSysが提供する回路図シンボル、PCBフットプリント、3D CADモデルがご確認いただけます。 お探しのシンボルやモデルが見つからない場合、Webサイトから直接リクエストできます。
| VFQFPN | 100 | I | Yes | Tray | 3 | 7.367 | サンプルを入手, | |
| VFQFPN | 100 | I | Yes | Reel | 3 | 7.12 |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
ビデオ&トレーニング
This video provides a brief comparison of PCIe Gen3-6 common clock jitter filters vs. a typical 12k to 20MHz jitter filter plot. The tutorial explains what noise frequencies PCIe Gen6 is most sensitive to, and why it's important to minimize jitter in the 1MHz to 50MHz region. Presented by Ron Wade, system architect at Renesas. For more information about Renesas’ PCIe timing solutions, visit renesas.com/pcietiming
ニュース＆ブログ
| ブログ | 2022年4月14日 | ||
| ブログ | 2022年4月14日 | ||
| ニュース | 2021年2月4日 | ||
| ブログ | 2018年5月22日 | ||
| ニュース | 2018年4月30日 |
