Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI
The evaluation board is designed to help the customer evaluate the 9ZXL1951D. The device is programmable through an SMBus interface. The user guide details the board...
概要
説明
The 9ZXL0851E is a second-generation enhanced performance DB800ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL0851A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.
特長
- LP-HCSL outputs with 85Ω Zout; eliminate 32 resistors, save 64mm² of area
- PCIe Gen 1–5 compliance
- 8 OE# pins; hardware control of each output
- Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz and 133.33MHz PLL mode; UPI and legacy QPI support
- 6mm × 6mm 48-VFQFPN package; small board footprint
製品比較
アプリケーション
アプリケーション
- Servers/High-performance Computing
- nVME Storage
- Networking
- Accelerators
- Industrial Control
設計・開発
ボード＆キット
モデル
ECADモデル
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Processing table
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ビデオ&トレーニング
PCIe Gen5 Clock Buffers
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.
Video List