Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI
The evaluation board is designed to help the customer evaluate the 9ZXL1951D. The device is programmable through an SMBus interface. The user guide details the board...
概要
説明
The 9ZXL0852E is a second-generation, enhanced-performance DB800ZL differential buffer. The part is pin-compatible with the 9ZXL0851A while offering a much-improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0852E has an SMBus Write Lockout pin for increased device and system security.
特長
- SMBus write lock feature; increases system security
- PCIe Gen 1–5 compliance
- LP-HCSL outputs with 85Ω Zout; eliminate 32 resistors, save 64mm² of area (0852E)
- 8 OE# pins; hardware control of each output
- Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz and 133.33MHz PLL Mode; UPI and legacy QPI support
- 6mm × 6mm 48-VFQFPN package; small board footprint
製品比較
アプリケーション
アプリケーション
- Servers/High-performance Computing
- nVME Storage
- Networking
- Accelerators
- Industrial Control
設計・開発
ボード＆キット
モデル
ECADモデル
[製品選択]テーブル内の製品名をクリックするとSamacSysが提供する回路図シンボル、PCBフットプリント、3D CADモデルがご確認いただけます。 お探しのシンボルやモデルが見つからない場合、Webサイトから直接リクエストできます。
Processing table
| VFQFPN | 48 | I | Yes | Tray | 3 | サンプルを入手, | ||
| VFQFPN | 48 | I | Yes | Reel | 3 |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
- Reset button in header: Reset all filters to the page default
- Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
ビデオ&トレーニング
PCIe Gen5 Clock Buffers
Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family.
For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page.
Video List