Processing table
Outputs (#) |
Inputs (#) |
Input Freq (MHz) |
DPLL Channels (#) |
JESD204B/C Compliant |
Output Freq Range (MHz) |
Frequency Plan |
Output Skew (ps) |
Adjustable Phase |
Noise Floor (dBc/Hz) |
Phase Noise Supports GSM |
Output Type |
Synthesis Mode |
Input Ref. Divider Resolution (bits) |
Feedback Divider Resolution (bits) |
Output Divider Resolution (bits) |
Supply Voltage (V) |
Input Redundancy |
Advanced Features |
Pkg. Type |
Lead Count (#) |
Price (USD) | 1ku |
|
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
型名 | ||||||||||||||||||||||
無線シンクロナイザ | 16 | 2 | 0.000001 - 1000 | 2 | Yes | 0.000001 - 1000 | 2500 / Output_Divider, 2949.12 / Output_Divider, 3670-3868 / Output_Divider | 74 | Yes | -165 | Yes | LVCMOS, LVDS, LVPECL | Fractional, Integer | 3 | 32 | 7 | 1.8, 2.5, 3.3 | Digital holdover, Hitless switch, Input Monitor, Phase-slope limiting | 1PPS, DCO, IEEE 1588, JESD204B, JESD204C, T-BC, T-TSC Class C, eEEC | VFQFPN | 88 | 23 |
JESD204B/C クロックジッタ減衰器 | 16 | 2 | 0.00375 - 2000 | 0 | Yes | 0.192 - 6000 | 3932.16 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 15 | 15 | 7 | 1.8, 2.5, 3.3 | Auto-switch, Holdover, Input Monitor, Manual input switch | Holdover, Input Switching, JESD204B | VFQFPN | 76 | 14.33 |
Clock Jitter Attenuator | 10 | 2 | 0.008 - 307.2 | 0 | No | 15.36 - 2949.12 | 2457.6 / Output_Divider, 2500 / Output_Divider, 2949.12 / Output_Divider | 41 | Yes | -161 | Yes | LVDS, LVPECL | Integer | 15 | 15 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 81 | 17.42 |
Clock Jitter Attenuator | 11 | 2 | 0.008 - 307.2 | 0 | No | 15.36 - 2949.12 | 2457.6 / Output_Divider, 2500 / Output_Divider, 2949.12 / Output_Divider | 28 | Yes | -158.7 | Yes | LVDS, LVPECL | Integer | 15 | 15 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, Phase Delay, Programmable Clock | CABGA | 81 | |
JESD204B/C Clock Jitter Attenuator | 12 | 2 | 0.008 - 250 | 0 | No | 15.625 - 2500 | 2400 / Output_Divider, 2500 / Output_Divider | 70 | Yes | -161 | Yes | LVDS, LVPECL | Fractional, Integer | 15 | 15 | 8 | 3.3 | Auto-switch, Input Monitor, Manual switch | Holdover, Input Switching, Phase Delay | CABGA | 81 | 21.66 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 30.72 - 500 | 0 | Yes | 20.48 - 1474.56 | 2949.12 / Output_Divider | 37 | Yes | -161 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | 26.05 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 12.288 - 1966.08 | 1966.08 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 15.36 - 2457.6 | 2457.6 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | 26.05 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | |
JESD204B/C Clock Jitter Attenuator | 15 | 2 | 1.92 - 2000 | 0 | Yes | 12.288 - 2457.6 | 2457.6 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | VFQFPN | 88 | |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 30.72 - 2000 | 0 | Yes | 18.432 - 3686.4 | 3686.4 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 | |
JESD204B/C クロックジッタ減衰器 | 15 | 2 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 0 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | VFQFPN | 88 | 13.12 |
JESD204B/C Clock Jitter Attenuator | 15 | 2 | 30.72 - 2000 | 0 | Yes | 19.6608 - 3932.16 | 3932.16 / Output_Divider | 100 | Yes | -160.2 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | VFQFPN | 88 | |
無線アクセスネットワーク機器用シンクロナイザ - 6チャネル | 24 | 10 | 0.001 - 1000 | 6 | Yes | 0.0000005 - 1000 | 50 | Yes | -158 | No | HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL | Fractional, Integer | 4 | 48 | 32 | 1.8, 2.5, 3.3 | Digital holdover, Hitless switch, Input Monitor, Phase-slope limiting | 1PPS, DCO, IEEE 1588, JESD204B, JESD204C, PWM Encoder/Decoder and more... |
VFQFPN | 72 |
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