R-Car V4H System Evaluation Board Set/White Hawk
The White Hawk is an R-Car V4H-specific evaluation board set that can be used to evaluate systems using the R-Car V4H and to develop operating systems, device drivers,...
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Overview
Description
The 9FGV0841 is an 8-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo=100 Ω. The device has 8 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
For information regarding evaluation boards and material, please contact your local IDT sales representative.
Features
- PCIe Gen1–4 compliant
- Integrated terminations provide 100Ω differential Zo: reduced component count and board space
- 1.8V operation: reduced power consumption
- Outputs can optionally be supplied from any voltage between 1.05V and 1.8V: maximum power savings
- OE# pins: support DIF power management
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- DIF outputs blocked until PLL is locked: clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins: SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 6 × 6 mm 48-VFQFPN; minimal board space
- Selectable SMBus addresses: multiple devices can easily share an SMBus segment
- Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version (wettable flank package)
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 348 KB | |
| Overview | PDF 2.40 MB | |
| Application Note | PDF 431 KB | |
| Application Note | PDF 91 KB | |
| Product Change Notice | PDF 734 KB | |
| Product Change Notice | PDF 728 KB | |
| Application Note | PDF 1.99 MB | |
| Product Change Notice | PDF 983 KB | |
| Schematic | PDF 79 KB | |
| Guide | PDF 321 KB | |
| Application Note | PDF 255 KB | |
| Product Change Notice | PDF 583 KB | |
| Application Note | PDF 307 KB | |
| Manual - Hardware | PDF 838 KB | |
| Product Change Notice | PDF 95 KB | |
| Product Change Notice | PDF 50 KB | |
| Application Note | PDF 235 KB | |
| Application Note | PDF 1.90 MB | |
| Application Note | PDF 495 KB | |
| Application Note | PDF 442 KB | |
| Application Note | PDF 233 KB | |
| Application Note | PDF 160 KB | |
| Application Note | PDF 120 KB | |
| Application Note | PDF 565 KB | |
| Product Change Notice | PDF 790 KB | |
| Application Note | PDF 136 KB | |
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Available on Lab on the Cloud
Use our PC-based GUI to instantly start configuring and testing designs in our virtual lab, no physical board needed.
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
Part Number
Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
News & Blog Posts
| Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System | Blog Post | Apr 14, 2022 |
| The Value of Fractional Output Divider PLLs for Infotainment and Dashboard Applications | Blog Post | Feb 7, 2019 |
| Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications | Blog Post | May 22, 2018 |
| IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices | News | Apr 30, 2018 |