概要
説明
The 6P61033 is an 8-output very-low power buffer for 100MHz PCIe Gen 1, Gen 2, and Gen 3 applications with integrated output terminations providing Zo = 100Ω. The device has eight output enables for clock management and three selectable SMBus addresses.
特長
- DIF cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 50ps
- DIF phase jitter is PCIe Gen 1-2-3 compliant
- Very-low additive phase jitter in bypass mode
- Integrated terminations provide 100Ω differential Zo reduced component count and board space
- 1.8V operation; minimal power consumption
- Outputs can optionally be supplied from any voltage between 1.05V and 1.8V; maximum power savings
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- LP-HCSL differential clock outputs; reduced power and board space
- Programmable slew rate for each output; allows tuning for various line lengths
- Programmable output amplitude; allows tuning for various application environments
- Pin/Software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Outputs are blocked until PLL is locked; clean system start-up
- Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications
- Configuration can be accomplished with strapping pins; SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 48-pin 6mm x 6mm VFQFPN; minimal board space
- Selectable SMBus addresses; multiple devices can easily share an SMBus segment
製品比較
アプリケーション
設計・開発
モデル
ECADモデル
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Processing table
| VFQFPN | 48 | I | Yes | Tray | ||
| VFQFPN | 48 | I | Yes | Reel |
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ビデオ&トレーニング
PCIe Clocking Architectures (Common and Separate)
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below
Video List
