ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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9FGV1008

アクティブ
2040 まで有効

Programmable PhiClock™ Generator

ご購入
9FGV1004C-9FGV1008C Datasheet

概要

The 9FGV1008 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1008 provides one integer frequency, one copy of a fractional or spread spectrum output frequency, and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components.

9FGV1004C_9FGV1008C - Block Diagram
9FGV1008C - Pinout
9FGV1004C_9FGV1008C - Block Diagram
9FGV1008C - Pinout
  • PCIe Gen1–4 compliant
  • 224fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
  • 2 programmable output pairs plus 1 LVCMOS REF output
  • 1 integer and 1 fractional or spread-spectrum output per configuration
  • 1MHz–325MHz integer outputs (LVDS or LP-HCSL)
  • 1MHz–200MHz integer outputs (LVCMOS)
  • 1.8V to 3.3V core VDD
  • Individual 1.8V to 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • Supports AC-coupled LVPECL and CML logic – see AN-891
  • 3 × 3 mm 16-LGA packages with 50MHz integrated crystal option
  • Supported by Timing Commander™ software

ドキュメント

設計・開発

ソフトウェアダウンロード
分類 タイトル 日時
ソフトウェア／ツール－その他
9FGV100x Integer v1.4.2 Timing Commander Personality File
ZIP 3.89 MB
ソフトウェア／ツール－ソフトウェア
I2C GUI Tool Software
ZIP 9.27 MB
2件
9FGV1008 - Evaluation Board (top)

EVK9FGV1008

Evaluation
詳しくはこちら

Evaluation Kit for 9FGV1008 Programmable PhiClock™ Generator

This is the evaluation board for the 9FGV1008 programmable PhiClockTM generator. It provides a convenient way of configuring and programming the blank parts for the

主要ドキュメント:
9FGV1006 / 9FGV1008 PhiClock PCIe Evaluation Board User Guide

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models
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製品選択

適用されたフィルター

ビデオ&トレーニング

PCIe Reference Clock Jitter Budgets

Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

Related Resources

 

Video List
PCIe Reference Clock Jitter Budgets
PCIe Data Rates vs Clock Jitter Specs
What Does PCIe Gen5 Say About SRIS?
IDT PhiClock™ PCIe Gen 4 Clock Generators, 9FGV100x Family
PCI Express (PCIe) Clock Overview by IDT
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling
PCI Express (PCIe) Clock Generators by IDT
PCI Express (PCIe) Clock Applications Overview
PCI Express Gen 1 to Gen 4/Gen 5 Data Rate Evolution
PCI Express Gen 1 to Gen 4/Gen 5 Clock Specification Evolution
PCI Express Common Clock Jitter Model and Transfer Functions

ニュース＆ブログ

Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System ブログ 2022年4月14日
Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility ブログ 2019年6月15日
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications ブログ 2018年5月22日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices ニュース 2018年4月30日